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| BU2381FV Multimedia ICs Clock generator for digital still camera BU2381FV BU2381FV is a high-performance 3-channel PLL IC. PLL circuit generates necessary clocks by inputting standard clocks of crystal oscillator from outside. Changing a connection of wire can generate any clocks required for any applications of users. Jitter and S/N characteristic has achieved almost the same high-quality sound and vision as oscillating module because of optimization of PLL. Frequency can be changed by the internal dividing control. Applications Digital still camera External dimensions (Unit : mm) 5.00.2 16 9 Features 1) Generate clocks for video output, CDS, USB from standard clock input 2) No external elements required for PLL 3) Standard clocks apply to two kinds of NTSC/PAL 4) Single power supply of 3.3V operating 5) SSOP-B16 small package 6.40.3 4.40.2 1 8 1.150.1 0.1 0.150.1 0.1 0.65 0.220.1 SSOP-B16 Absolute maximum ratings (Ta=25C) Parameter Applied voltage Input voltage Storage temperature range Power dissipation Symbol VDD VIN Tstg Pd Limits -0.5 to +7.0 -0.5 to VDD+0.5 -30 to +125 450 Unit V V C mW Derating : 4.5mW/C for operating above Ta=25C An operation is not guaranteed. Radiation resistance design is not used. Power dissipation is measured when BU2381FV is placed on the board. Recommended operating conditions (Ta=25C) Parameter Supply voltage Input "H" voltage range Input "L" voltage range Operation temperature range Output maximum load Symbol VDD VIH VIL Topr CL Min. 3.0 0.8VDD 0 -5 - Typ. - - - - - Max. 3.6 VDD 0.2VDD 70 15 Unit V V V C pF 0.3Min. 1/5 BU2381FV Multimedia ICs Block diagram Data1a Data1b Data1c 71.877274MHz or 90.314686MHz or 114.54546MHz PLL1 144M 180M 228M 1/2 CLK1 96.016044MHz 1/2 14.318182MHz XTAL_IN XTAL_OUT XTAL OSC PLL2 192MHz 1/2 96.016044MHz CLK2 48.008022MHz 1/4 CLK2ON PLL3 177MHz 17.734450MHz FS1 1 / 10 REF_CLK FS2 14.318182MHz FS3 Pin descriptions Pin No. 1 2 3 4 5 6 7 8 9 10 11 12 13 14 15 16 Pin name REFCLK VDD FS3 VSS XIN TEST XOUT FS2 CLK1OUT FS1 CLK2ON VSS VDD CLK2OUT VSS VDD Functions 14.3MHz / 17.7MHz clock output Analog VDD CLK1, 2 output select with pull up Analog GND Standard crystal input Input for test mode (normally open) Standard crystal output CLK1, 2 output select with pull up 71M / 90M / 96M / 114MHz clock output REFCLK output select with pull up CLK2 output control with pull up H : enable L : disable GND for CLK1, 2 clock output and Logic circuit VDD for CLK1, 2 clock output and Logic circuit 96M / 48M clock output GND for REFCLK clock output VDD for REFCLK clock output 2/5 BU2381FV Multimedia ICs Input output circuits Pin No. Equivalent circuit Input PIN 3, 8, 10, 11 To inside IC with pull-up (PIN6 : TESTpin with pull down) OUTPUT PIN 1, 9, 14 From inside IC Crystal PIN 5, 7 XTALIN XTALOUT To inside IC 3/5 BU2381FV Multimedia ICs Electrical characteristics (Unless specified otherwise Ta=25C, VCC=3.3V) Parameter Power supply current Output frequency FS2 : H FS3 : H FS2 : H FS3 : L FS2 : L FS3 : L FS2 : L FS3 : H FS2 : L FS3 : L FS2, 3 : HL / LH / HH FS1 : H FS1 : L Symbol IDD - Fclk1-1 Fclk1-2 Fclk1-3 Fclk1-4 Fclk2-1 Fclk2-2 Fref1-1 Fref1-2 Duty1 Duty2 tr tf P-J1 P-JMINMAX Tlock Min. - - - - - - - - - - 45 - - - - - - Typ. 40 - 96.016044 71.877274 114.54546 90.314686 96.016044 48.008022 14.318182 17.73445 50 50 2.5 2.5 30 180 - Max. 50 - - - - - - - - - 55 - - - - - 1 Unit mA - - - MHz MHz MHz MHz MHz MHz % % nsec nsec psec psec msec Xtal (228 / 17) / 2 Xtal (251 / 25) / 2 Xtal (224 / 14) / 2 Xtal (164 / 12) / 2 Xtal (228 / 17) / 2 Xtal (228 / 17) / 4 Crystal direct output Xtal (706 / 57) / 10 Measured at 1/2 VDD Measured at 1/2 VDD Time between 0.2 VDD and 0.8 VDD Time between 0.8 VDD and 0.2 VDD 1 2 3 No load Conditions CLK1 CLK2 REFCLK Duty1 at 100MHz Duty2 at 100MHz Rise time Fall time Period jitter 1 Period jitter MIN-MAX Output Lock time Note) When input frequency is 14.318182MHz, output frequency is above rated value. 1) Period Jitter 1 : This value is the standard deviation of an output period when using Time Interval Analyzer with 10,000 sampling. 2) Period Jitter MIN-MAX : This value is the max range of an output period when using Time Interval Analyzer with 10,000 sampling. 3) Output Lock time : This value is the time until the output clock gets stable after the power supply voltage leads to 3.0V. 4/5 BU2381FV Multimedia ICs Application example REFCLK output 1 16 0.1F 2 FS3 H or L 15 CLK2 output 3 0.1F 14 4 13 0.1F 5 12 CLK2 ON H or L 6 11 7 FS2 H or L 10 FS1 H or L CLK1 output 8 9 Note) The BU2381FV is placed on the board normally. A decoupling capacitor (0.1F) needs to be placed between pin2 and pin4, pin13 and pin12, pin16 and pin15. The decoupling capacitor is an close to the above pins as possible. 5/5 |
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